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<p>This International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently.</p>
<p>The contents given in this specifications are as follows:</p>
<p>a) System bus interface signal provisions;</p>
<p>b) Bus operations and transfer protocol for each bus operation; </p>
<p>c) Copyback cache coherency control for maintaining consistency between a shared memory and a cache memory of each processor in a multiprocessor system;</p>
<p>d) Fault detection function using parity check and duplex configuration for control signals.</p>
Reģistrācijas numurs (WIID)
24837
Darbības sfēra
<p>This International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently.</p>
<p>The contents given in this specifications are as follows:</p>
<p>a) System bus interface signal provisions;</p>
<p>b) Bus operations and transfer protocol for each bus operation; </p>
<p>c) Copyback cache coherency control for maintaining consistency between a shared memory and a cache memory of each processor in a multiprocessor system;</p>
<p>d) Fault detection function using parity check and duplex configuration for control signals.</p>
